UVM Coding Practice · Senior

Reg Block & Field Access

uvm_reg_block, fields, frontdoor access.

Interview prompt

Sketch reg block with one CTRL reg RW and STATUS RO field.

diagram

WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog

class ctrl_reg extends uvm_reg;
  rand uvm_reg_field enable;
  function void build();
    enable = uvm_reg_field::type_id::create("enable");
    enable.configure(this, 1, 0, "RW", 0, 0, 1, 0, 1);
  endfunction
endclass

class blk extends uvm_reg_block;
  ctrl_reg CTRL;
  function void build();
    default_map = create_map("map", 0, 4, UVM_NO_ENDIAN, 4);
    CTRL = ctrl_reg::type_id::create("CTRL");
    CTRL.configure(this);
    CTRL.build();
    default_map.add_reg(CTRL, 0, "RW");
    lock_model();
  endfunction
endclass

Mechanism to narrate

uvm_reg_block owns registers and address map
Fields have access policy RW/RO/WO
lock_model() after build — required before use

Smoke test (5 minutes)

Narrate frontdoor write to CTRL.enable field.
Explain why STATUS field is RO on read path.

Common pitfalls

Forget lock_model.
Wrong field width in configure.
Skip default_map.

Practice this lesson