UVM Coding Practice · Senior
Phases Tricky Q&A
20 phase/objection interview questions.
Q&A bank
Phases/objections interview bank.
Sim hang after test?
diagram
[INT][SENIOR][UVM-CODE]
Q: Sim hang after test?
A:
Objection leak — count > 0. Check raise/drop pairs.
FOLLOW-UP TRAP: Assume driver bug first.Too many objections?
diagram
[INT][SENIOR][UVM-CODE]
Q: Too many objections?
A:
Multiple raises without drop — same fix.
FOLLOW-UP TRAP: Lower timeout only.raise_objection where?
diagram
[INT][SENIOR][UVM-CODE]
Q: raise_objection where?
A:
test.run or seq pre_start; drop in post_body or test end.
FOLLOW-UP TRAP: raise in driver.drain_time?
diagram
[INT][SENIOR][UVM-CODE]
Q: drain_time?
A:
set_drain_time before drop_all — allow DUT pipeline flush.
FOLLOW-UP TRAP: Zero drain on pipelined DUT.phase jump risks?
diagram
[INT][SENIOR][UVM-CODE]
Q: phase jump risks?
A:
Skip cleanup phases — resources left active.
FOLLOW-UP TRAP: Jump to skip slow sim always.domain sync?
diagram
[INT][SENIOR][UVM-CODE]
Q: domain sync?
A:
uvm_domain sync between clock domains for phase alignment.
FOLLOW-UP TRAP: Async domains same phase schedule.run-time sub-phases?
diagram
[INT][SENIOR][UVM-CODE]
Q: run-time sub-phases?
A:
reset, configure, main, shutdown in UVM 1.2 run_phase.
FOLLOW-UP TRAP: Everything in one run task.reset_phase vs run_phase?
diagram
[INT][SENIOR][UVM-CODE]
Q: reset_phase vs run_phase?
A:
reset_phase for reset tasks; run for main stimulus.
FOLLOW-UP TRAP: Reset in run forever.Objection in sequence?
diagram
[INT][SENIOR][UVM-CODE]
Q: Objection in sequence?
A:
seq raises/drops or test only — pick one policy.
FOLLOW-UP TRAP: Both raise — double count.super.build_phase order?
diagram
[INT][SENIOR][UVM-CODE]
Q: super.build_phase order?
A:
super first or last — team convention for children create.
FOLLOW-UP TRAP: Random super call placement.connect before run?
diagram
[INT][SENIOR][UVM-CODE]
Q: connect before run?
A:
connect_phase wires TLM; run drives/monitors.
FOLLOW-UP TRAP: Connect in run_phase.Phase callback?
diagram
[INT][SENIOR][UVM-CODE]
Q: Phase callback?
A:
phase_started for debug — rare in interviews.
FOLLOW-UP TRAP: Heavy work in callback.10-min objection sketch?
diagram
[INT][SENIOR][UVM-CODE]
Q: 10-min objection sketch?
A:
timeline: raise at test start, drop after seq, drain_time.
FOLLOW-UP TRAP: No timeline drawn.UVM_MEDIUM quit count?
diagram
[INT][SENIOR][UVM-CODE]
Q: UVM_MEDIUM quit count?
A:
Test level max quit — separate from objections.
FOLLOW-UP TRAP: Confuse error quit with hang.main_phase default?
diagram
[INT][SENIOR][UVM-CODE]
Q: main_phase default?
A:
Most stimulus in main_phase task.
FOLLOW-UP TRAP: main in build.shutdown_phase?
diagram
[INT][SENIOR][UVM-CODE]
Q: shutdown_phase?
A:
Wait for idle, report summary.
FOLLOW-UP TRAP: Skip shutdown always.Parallel objections?
diagram
[INT][SENIOR][UVM-CODE]
Q: Parallel objections?
A:
Multiple components raise — all must drop.
FOLLOW-UP TRAP: Test drops one only.fork join in run_phase?
diagram
[INT][SENIOR][UVM-CODE]
Q: fork join in run_phase?
A:
Join before phase ends or use separate objections per branch.
FOLLOW-UP TRAP: Orphan fork.Phase debug?
diagram
[INT][SENIOR][UVM-CODE]
Q: Phase debug?
A:
UVM_PHASE_TRACE or objection trace.
FOLLOW-UP TRAP: Blind wait forever.Clock generator phase?
diagram
[INT][SENIOR][UVM-CODE]
Q: Clock generator phase?
A:
start forever in run or before run in initial — document.
FOLLOW-UP TRAP: Stop clock on phase end wrong.