UVM Coding Practice · Senior

Factory set_type_override

Override order before create.

Interview prompt

Override pkt base with derived_pkt for all creates in test.

diagram

WHITEBOARD CHAIN

1. DECLARE    interfaces / types / ports you need
2. SKELETON   class extends + utils macro + key methods
3. MECHANISM  fill one critical method while narrating
4. PITFALL    name one bug juniors make on this pattern
5. TEST       how you would smoke-test the component

Reference sketch (≤40 lines)

systemverilog

function void build_phase(uvm_phase phase);
  pkt::type_id::set_type_override(derived_pkt::get_type());
  super.build_phase(phase);
endfunction

Buggy snippet — critique verbally

systemverilog

env = env_type::create("env"); // override after create — too late
pkt::type_id::set_type_override(derived_pkt::get_type());

Code lab drill

After reading, try Code lab exercise uvm-l8-int-factory — topic reference: /topics/uvm/coding-practice/factory-config/factory-set-type-overrides

Practice this lesson