Debug and ECO interviews test judgment with evidence: where unknowns come from, why passing simulations still fail in silicon, how intermittent bugs get captured, and when a late fix is a gate edit or an RTL change.
4 lessons, about 17 min
Check the first divergence, not the last symptom. Every lesson in this topic is that habit applied to a different gap.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
X-propagation discipline
X comes from uninitialised flops, incomplete reset, undefined memories and powered-down domains.
An X select takes the else branch of an if, holds the old value in a case, and gives X from a ternary with disagreeing inputs.
X means unknown, not don't care. Silicon picks a real value the testbench never checked.
Rule of thumb: close every X at its source: reset it, define it, or clamp it.
Why simulation and silicon disagree
Every gap has one shape: the simulator models something silicon does not honour.
Model gaps far outnumber tool bugs, so audit the model before blaming the tool.
A wrong constraint or an unconstrained crossing makes STA check something other than the hardware.
Rule of thumb: name the idealisation first, then add the check that removes it.
Capturing an intermittent failure
A seed alone is not a run configuration. Record source revision, tools, defines, parameters, inputs and reset schedule.
Trigger on the earliest divergence and keep pre-trigger history in a circular buffer. Dumping after the failure loses causes.
Vary one knob at a time and halve the stimulus until the failure fits in one wave window.
Rule of thumb: seed it, trigger on the first divergence, halve until small.
ECO or RTL change
Check the constraint first. A wrong clock definition gives a violation the hardware never sees.
A single failing path takes a local gate edit. A structural shortfall across many paths takes an RTL change.
Fix setup and hold together, and close an ECO with equivalence, regressions and all timing views.
Rule of thumb: repeated ECOs on the same logic mean the structure is wrong.
Mini project: the capstone: a resilient streaming peripheral, stage by stage
Practice question: 3-to-8 decoder: unique/priority case and X-propagation
Code lab: X-propagation model
Interview: run a mock interview on this topic