Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
    • Writing Properties That Can Fail and Say Something
    • Assumptions as a Contract
    • Abstraction and Complexity
    • Assume-Guarantee and Black Boxes
    • Reusable Property Sets
      • Checker Modules and Wrapper Harnesses
      • Parameterised Property Sets
      • Property Sets for the Running Designs
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
  • Formal Coverage and Signoff15
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
Loading lesson

←Property Development and Constraints
  1. Topics
  2. Formal Verification
  3. Property Development and Constraints
  4. Reusable Property Sets

Part 3 of 10Part 3 of 10/Property Development and ConstraintsAll levels

Reusable Property Sets

Write a property set once as a checker module, prove it at several sizes and modes, and keep a table of the rules for each running design.

  • 3topics
  • 3lessons

A property library pays for itself when the same rule is checked on the other face of an interface, at another size or in another mode. It fails when the library is wrong about roles, when the sizes it was proved at are too small to show the faults, or when its rule table has rules with no cover. This topic builds one checker used on two faces of the bridge, proves a parameterised design at several sizes and modes, and ends with the rule tables of three running designs checked mechanically.

Lesson

After it you can...

Checker Modules and Wrapper Harnesses

Write one checker with a role parameter and instantiate it as an assumption on one face and an assertion on the other.

Parameterised Property Sets

Prove at the sizes and modes that expose faults, and state the depth a bounded run needs.

Property Sets for the Running Designs

Keep a rule table whose asserts and antecedent covers are checked against the design files.

Suggested order: top to bottom. The checker is the unit of reuse, parameters and modes are the axis of reuse, and the rule tables record what the library covers.

A checker box above two boxes: the upstream face where the rule is assumed and the downstream face where it is asserted.
One checker module, two roles: the role parameter makes it an assumption on the face the design receives and an assertion on the face it drives.
Check yourself Why must the same checker be an assumption on one face and an assertion on the other?

The rule is owed by the block that drives a face and assumed by the block that receives it. An assertion on a free input fails at once; an assumption on an output prunes the design.

Be ready to answer: which sizes and modes did you prove this at, and why are they enough? Name the smallest size that shows each fault and the mode whose cover is reached.

Related topics

  • Up: Property Development and Constraints

  • SystemVerilog: SVA Checker Libraries

PreviousNext: Checker Modules and Wrapper Harnesses

Up next

Up nextChecker Modules and Wrapper Harnesses

Sign in to save progress

Practice this lessonPrevious lessonReport an error

See also

  • Writing Properties That Can Fail and Say Something
  • Assumptions as a Contract
  • Abstraction and Complexity