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Course contents

  • How to Use This Course
  • Reading Paths
  • Glossary
  • Metrics Reference
  • Formal Cheat Sheet
  • Formal Foundations19
  • Properties and SVA16
  • Property Development and Constraints19
  • Proof Engines and Convergence23
  • Formal Applications20
  • Equivalence Checking14
  • Formal Coverage and Signoff15
    • Cover Properties, Vacuity and Reachability
      • Antecedent Covers and Witness Traces
      • Over-Constraint Seen Through Covers
      • Bounded Cover Miss Is Inconclusive
      • Vacuity by Mutation and Sensitivity
    • Formal Coverage Metrics
    • Bounded Proof Signoff
    • The Formal Signoff Package
  • Methodology and Debug13
  • Interview Prep15
  • Capstone: A Chip-Block Verification Lab24
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←Formal Coverage and Signoff
  1. Topics
  2. Formal Verification
  3. Formal Coverage and Signoff
  4. Cover Properties, Vacuity and Reachability

Part 7 of 10Part 7 of 10/Formal Coverage and SignoffAll levels

Cover Properties, Vacuity and Reachability

Every implication gets a cover of its trigger, so a passing proof is never an empty promise.

  • 4topics
  • 4lessons

A passing property can be a lie with a straight face. The trigger never fires, the environment never offers the interesting case, or the check compares a signal with itself, and the report still says pass. This topic makes every pass earn its keep: each implication gets a cover of its trigger, each cover gets a witness trace that you read, and any required scenario that cannot be reached fails sign-off outright. The running examples are the four-requester arbiter and the skid-buffer bridge, plus one dead trigger that passes and is caught.

Lesson

After it you can...

Antecedent Covers and Witness Traces

Pair every implication with a trigger cover and read the witness cycle by cycle.

Over-Constraint Seen Through Covers

Spot a strangled environment from its silent covers and repair the harness.

Bounded Cover Miss Is Inconclusive

Word the three cover outcomes correctly and prove unreachability when you claim it.

Vacuity by Mutation and Sensitivity

Catch a check that cannot fail by mutating the design and the property.

Suggested order: top to bottom. Antecedent covers first, because they are the habit everything else builds on; over-constraint next, because it is the commonest reason covers go quiet; the bounded-miss wording next, because it stops a quiet cover being misread; mutation last, because it catches the vacuity that covers alone miss.

A cover result has two first outcomes: reached, which gives a witness that is read, or not reached within the bound. A miss is inconclusive and demands more work; only an invariant proof turns it into proved unreachable.
What each cover outcome means and what it demands next.
Check yourself A property passes and its trigger cover is unreached. Has the property told you anything about the design?

No. The check never fired, so the design could be arbitrarily broken in the covered behaviour. Treat the pair as a failure of the verification, not as evidence.

Related topics

  • Next: Antecedent Covers and Witness Traces

  • SystemVerilog: Vacuous Passes

  • SystemVerilog: Debugging Passes

PreviousNext: Antecedent Covers and Witness Traces

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See also

  • Formal Coverage Metrics
  • Bounded Proof Signoff
  • The Formal Signoff Package