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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
    • Graph Traversal & Slack
    • Cell vs Net Delay Budgets
      • Where the Delay Goes
      • Sizing and Delay Sensitivity
      • Wire Load and Routed Parasitics
      • Budgeting a Path
    • Path Group Prioritization
    • Report Timing Deep Read
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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←Cell vs Net Delay Budgets
  1. Topics
  2. Static Timing Analysis
  3. Delay Graph & Path Analysis
  4. Cell vs Net Delay Budgets
  5. Budgeting a Path
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    Part 3 of 11, lesson 8 of 16Part 3 of 11/Delay Graph and Path Analysis/Lesson 8 of 16All levels

    Budgeting a Path

    A path budget assigns each stage a delay allowance that sums to less than the period, so teams can design and fix against numbers.

    Why it matters

    A budget turns "this path must meet 2 ns" into a list of allowances per stage. It lets RTL, synthesis and physical design agree on targets, and it makes a violation easy to localise: the stage that exceeded its allowance.

    Building one

    Stage

    Budget (ns)

    Actual (ns)

    Over?

    Clock-to-Q

    0.40

    0.40

    Logic stage 1

    0.45

    0.52

    +0.07

    Wire 1

    0.15

    0.14

    Logic stage 2

    0.45

    0.44

    Wire 2

    0.15

    0.20

    +0.05

    Setup

    0.10

    0.10

    Margin

    0.30

    -

    -

    example.py
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    T = 2.0
    budget = {"cq": 0.40, "logic1": 0.45, "wire1": 0.15, "logic2": 0.45, "wire2": 0.15, "setup": 0.10}
    actual = {"cq": 0.40, "logic1": 0.52, "wire1": 0.14, "logic2": 0.44, "wire2": 0.20, "setup": 0.10}
    assert abs(sum(budget.values()) - 1.70) < 1e-9
    margin = T - sum(budget.values())
    assert abs(margin - 0.30) < 1e-9
    over = {k: round(actual[k] - budget[k], 2) for k in budget if actual[k] > budget[k] + 1e-9}
    assert over == {"logic1": 0.07, "wire2": 0.05}
    slack = T - sum(actual.values())
    assert abs(slack - 0.20) < 1e-9
    print("PASS: budget margin", round(margin, 2), "actual slack", round(slack, 2), "over-budget stages", over)

    The budget sums to 1.70 ns, leaving 0.30 ns of margin in a 2.0 ns period. The actual path sums to 1.80 ns, so slack is 0.20 ns, still positive even though two stages exceeded their allowances (by 0.07 and 0.05 ns). The budget shows who owns the overrun and how much margin remains, which the total alone does not. The budget assumes ideal clocks: clock uncertainty and skew are not separate stages and are covered by the margin.

    What the review looks for

    • Budgets are agreed across teams before implementation and revised in the open when a stage cannot meet its allowance.

    • Margin is explicit and owned (not hidden in stage allowances), and shrinks as the design matures.

    • Overruns are tracked per stage so repeated offenders (a macro, a bus) are found.

    Budgeting with typical numbers. Budgets must use signoff-corner values (or a defined correlation to them); a budget in the typical corner produces failures when signoff numbers arrive.

    Walk a budget table and say what margin means: the unallocated part of the period, owned by someone and consumed deliberately.

    Check yourself In the table, which stages exceed their budget, and is the path failing?

    Logic stage 1 (+0.07) and wire 2 (+0.05). The path is not failing: total actual 1.80 ns against a 2.0 ns period leaves +0.20 ns, because the margin absorbed the overruns.

    Related topics

    • Wire Load and Routed Parasitics

    • Interface Budgets

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    See also

    • Where the Delay Goes
    • Sizing and Delay Sensitivity