Low Power Verification · All levels

Level-Shifter Direction, Threshold, and Enable Checks: Debug Playbook

Debug Playbook for Level-Shifter Direction, Threshold, and Enable Checks.

Debug playbook

Debug Playbook for Level-Shifter Direction, Threshold, and Enable Checks is anchored on Illegal voltage-direction crossing count and level-shifter control-sequence violations across static signoff and dynamic low-power regressions.. Convert observations into mechanism-backed and owner-bound actions.

Freeze seed, metadata, and boundary under investigation.
Locate first persistent low-power phase divergence.
Classify mechanism: setup, transition, boundary, retention, or X-prop class.
Apply one focused reproducer and one bounded fix.
Re-run determinism and broader regression matrix.

Review memo template

diagram

LPV REVIEW MEMO - Isolation & Level Shifting / Level-Shifter Direction, Threshold, and Enable Checks

1. Symptom
   - Failing metric: Illegal voltage-direction crossing count and level-shifter control-sequence violations across static signoff and dynamic low-power regressions.
   - Trigger context: <seed/mode/sequence>
   - First failing phase: <entry/off/exit/boundary>

2. Mechanism hypothesis
   - Candidate mechanism: Level-shifter verification must establish that every voltage-domain crossing uses the right cell type and orientation for the source-to-destination voltage relationship. High-to-low paths may tolerate direct receive cells in specific libraries, but low-to-high paths typically require explicit up-shifters to satisfy VIH thresholds and avoid metastable interpretation in destination flops. Direction checks alone are insufficient: many implementations use enabled level shifters, so verification must prove enable pins are driven from valid always-on control sources, assert early enough during ramp transitions, and never glitch during domain state changes. Engineers should also validate exceptions such as analog wrappers, open-drain signals, and scan/test bypasses, where policy deviations are intentional but still require documented justification and dedicated assertions.
   - Competing hypotheses: setup, transition race, boundary bug, retention drift, X-prop noise
   - Missing evidence: <trace/assertion/report>

3. Proposed action
   - Smallest reversible change: <intent/RTL/checker/flow>
   - Expected movement: <failure trend/replay stability>
   - Regression risk: compatibility, coverage, signoff delay

4. Signoff
   - Required artifact: Cross-domain voltage-compatibility report with shifter direction rules, enable-timing waveforms, and approved exception ledger.
   - Required owners: library and circuit integration owner, low-power architecture owner, implementation/PD owner, power intent verification owner, DFT and test integration owner
   - Final decision: ship, bounded rollout, rollback, or escalate

Low-power verification deep dive

Boundary correctness depends on timing: isolate and shift at the right crossings and right phases.

Concept diagram

diagram

BOUNDARY SAFETY VIEW

domain crossing -> level-shift requirement -> isolation control -> OFF/ON transition behavior

Metric graph

diagram

BOUNDARY BUG CLASSES

missing isolation      █████
late isolation         ████
LS misdirection        ███

Metrics and artifacts to collect

cross-domain boundary inventory
clamp-value correctness report
LS direction and threshold checks
missing or redundant boundary action list

Mini case study

A boundary bug escaped unit tests until domain-off traffic stress revealed late isolation enable timing.

Debug branches

Map each crossing to expected LS and isolation behavior.
Verify enable timing against collapse and restore edges.
Check clamp safety for protocol-facing signals.

Senior review question

Ask: what exact low-power transition boundary failed first, and which artifact proves the closure claim reproducibly?

Key takeaways

Tie each LPV claim to a concrete transition boundary and one proving artifact.
Prefer minimal reversible fixes with explicit owner and rollback criteria.

Common pitfalls

Treating power-aware failures as random before boundary classification.
Waiving X-prop failures before proving impact and root cause.
Declaring closure without deterministic replay across key modes.

Debug ladder

Sequence: reproduce -> classify -> isolate boundary -> prove mechanism -> bounded fix.

Avoid mixed fixes before first-principles classification.

Practice this lesson