Test Logic Floorplan

What this topic teaches

Test Logic Floorplan turns DFT intent into measurable release confidence. Placement of decompressors, compactors, and BIST controllers impacts routing quality, clocking, and timing closure effort. The senior challenge is proving whether a metric move came from real quality gain, setup drift, or hidden regression.

The senior-engineer question

When compression logic placement quality, test route detours, floorplan DFT ECO count moves, can you identify mechanism, evidence quality, owner, and the minimum safe next action?

DFT CLOSURE FLOW - Test Logic Floorplan

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Picture the closure flow

Draw the causal flow before opening tools. Use these diagrams to anchor architecture, constraints, and silicon behavior discussions.

Compression logic placement

decompressor/compactor placement too far from chains
  -> detours + skew + route pressure

Process sequence

DFT FLOW - Test Logic Floorplan

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO count

Ownership layers

DFT OWNERSHIP LAYERS - Test Logic Floorplan

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

Evidence to collect

• Primary metric: compression logic placement quality, test route detours, floorplan DFT ECO count.

• Primary artifact: test logic floorplan review, placement snapshots, routing detour report.

• Owners to bring into review: PD owner, DFT owner, CTS owner.

• One failing signature and one reduced reproduction path.

• Exact run tags for constraints, patterns, and tester program.

Ownership map

OWNERSHIP MAP - Test Logic Floorplan

artifact              owner
----------------      -----------------
architecture/report PD owner
constraints/setup   DFT owner
physical/test       CTS owner

Name an owner for each failing metric cluster.

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• State metric and run tags with every claim.

• Connect every fix to a regression matrix.

• Treat quality, timing, and power as coupled.

Common pitfalls

• Coverage-centric decisions without legality checks.

• Pattern changes without tester correlation.

• Release calls without owner signoff.

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.