Virtual Memory and the TLB · arch

Computer ArchitectureAll levels

Every load and store uses a virtual address. A page table translates each page to physical memory, and a TLB caches recent translations.

Term	Meaning
Page	A fixed-size, aligned block of virtual address space, commonly 4 KiB.
VPN / PPN	Virtual and physical page numbers: the address with the page offset removed.
PTE	A page-table entry: the PPN plus present, permission, accessed and dirty bits.
Walk	The sequence of table reads that resolves one VPN on a TLB miss.
TLB reach	Entries times page size: the memory mapped without revisiting the table.
ASID	An address-space tag so entries from several processes share the TLB.

Translation path with TLB hit and miss.

A TLB hit translates in one step; a miss walks the page table first.

Lesson	What it covers
Pages and multi-level walks	Page format, four-level tables, and a worked address split.
TLB reach and miss cost	TLB organization, reach arithmetic, and average translation cost.
Huge pages	2 MiB and 1 GiB pages: shorter walks, larger reach, fragmentation cost.
Translation and cache indexing	VIPT caches and the size rule that keeps the index translation-free.

Check yourself A TLB miss still returns the right data, just slower. What does that say about what the TLB is?

It is a cache of translations, not the translation itself. The page table holds the mapping; the TLB only avoids re-walking it.