Combinational & Sequential Logic

A | B | AND | OR | XOR | NAND
--|---|-----|----|----|-----
0 | 0 |  0  | 0  | 0  |  1
0 | 1 |  0  | 1  | 1  |  1  
1 | 0 |  0  | 1  | 1  |  1
1 | 1 |  1  | 1  | 0  |  0

// 4-to-1 Multiplexer
module mux_4to1 (
  input  logic [3:0] data_in,
  input  logic [1:0] select,
  output logic data_out
);

always_comb begin
  case (select)
    2'b00: data_out = data_in[0];
    2'b01: data_out = data_in[1];
    2'b10: data_out = data_in[2];
    2'b11: data_out = data_in[3];
  endcase
end

endmodule

D FF | Clk | Q(next)
-----|-----|--------
  0  | ↑   |   0
  1  | ↑   |   1
  X  | 0/1 | Q(prev)

// 4-bit Counter with Load
module counter_4bit (
  input  logic clk, rst_n,
  input  logic load, enable,
  input  logic [3:0] load_data,
  output logic [3:0] count
);

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    count <= 4'b0000;
  else if (load)
    count <= load_data;
  else if (enable)
    count <= count + 1;
end

endmodule

Full Adder
A | B | Cin | Sum | Cout
--|---|-----|-----|-----
0 | 0 |  0  |  0  |  0
0 | 0 |  1  |  1  |  0
0 | 1 |  0  |  1  |  0
1 | 1 |  1  |  1  |  1

// 4-bit Ripple Carry Adder
module ripple_carry_adder_4bit (
  input  logic [3:0] a, b,
  input  logic cin,
  output logic [3:0] sum,
  output logic cout
);

logic [2:0] carry;

// Full adder instances
full_adder fa0 (.a(a[0]), .b(b[0]), .cin(cin),     .sum(sum[0]), .cout(carry[0]));
full_adder fa1 (.a(a[1]), .b(b[1]), .cin(carry[0]), .sum(sum[1]), .cout(carry[1]));
full_adder fa2 (.a(a[2]), .b(b[2]), .cin(carry[1]), .sum(sum[2]), .cout(carry[2]));
full_adder fa3 (.a(a[3]), .b(b[3]), .cin(carry[2]), .sum(sum[3]), .cout(cout));

endmodule

// Full Adder Module
module full_adder (
  input  logic a, b, cin,
  output logic sum, cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));

endmodule